The present invention relates generally to logic circuits and, more particularly, to half-rail differential logic circuits.
With the emergence of an electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation, a demand has arisen for low power circuits and systems. This demand has motivated circuit designers to depart from conventional circuit designs and venture into more power efficient alternatives. As part of this effort, half-rail differential logic has emerged as an important design tool for increasing power efficiency.
FIG. 1A shows a schematic diagram of one embodiment of a clocked half-rail differential logic circuit 100 designed according to the principles of the invention set forth in patent application Ser. No. 09/927,751, entitled xe2x80x9cClocked Half-Rail Differential Logicxe2x80x9d, filed Aug. 9, 2001, in the name of the present inventor, assigned to the assignee of the present invention, and incorporated herein by reference, in its entirety. As seen in FIG. LA, a clock signal CLK is coupled to an input node 132 of a clock inverter 134 to yield a clock-not signal CLKBAR at output node 136 of clock inverter 134.
As also seen in FIG. 1A, clocked half-rail differential logic circuit 100 includes a first supply voltage 102 coupled to a source, or first flow electrode 130, of a PFET 101. The signal CLKBAR is coupled to a control electrode or gate 103 of PFET 101 and a control electrode or gate 129 of an NFET 109. A drain, or second flow electrode 104, of PFET 101 is coupled to both a source, or first flow electrode 106, of a PFET 105 and a source, or first flow electrode 108, of a PFET 107. A control electrode or gate 116 of PFET 105 is coupled to a first flow electrode 140 of NFET 109 and an OUTBAR terminal 113. A control electrode or gate 114 of PFET 107 is coupled to a second flow electrode 138 of NFET 109 and an OUT terminal 111. A drain, or second flow electrode 110, of PFET 105 is coupled to OUT terminal 111 and a drain, or second flow electrode 112, of PFET 107 is coupled to OUTBAR terminal 113.
OUT terminal 111 is coupled to a terminal 118 of a base logic portion 123A of a logic block 123 and OUTBAR terminal 113 is coupled to a terminal 120 of a complementary logic portion 123B of logic block 123. Base logic portion 123A of logic block 123 includes any type of differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. Complementary logic portion 123B of logic block 123 includes any type of complementary differential logic and/or circuitry used in the art including various logic gates, logic devices and circuits. As discussed in more detail below, since clocked half-rail differential logic circuit 100 was a dual rail logic circuit, requiring an output OUT 111 and a complementary output OUTBAR 113, in the prior art, logic block 123 had to include both a base logic portion 123A, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic portion 123B of base logic portion 123A, such as a NAND gate, NOR gate, XNOR gate, etc. Logic block 123 also includes first and second input terminals 151 and 153 that are typically coupled to an OUT and OUTBAR terminal of a previous clocked half-rail differential logic circuit stage (not shown).
Logic block 123 also includes fourth terminal 122 coupled to a drain, or first flow electrode 124, of an NFET 125. A gate or control electrode 127 of NFET 125 is coupled to the signal CLK and a source, or second flow electrode 126, of NFET 125 is coupled to a second supply voltage 128.
A particular embodiment of a clocked half-rail differential logic circuit 100 is shown in FIG. 1A. Those of skill in the art will recognize that clocked half-rail differential logic circuit 100 can be easily modified. For example, different transistors, i.e., first, second and third PFETs 101, 105 and 107 or first and second NFETs 109 and 125 can be used. In particular, the NFETs and PFETS shown in FIG. 1A can be readily exchanged for PFETs and NFETs by reversing the polarities of the supply voltages 102 and 128, or by other well known circuit modifications. Consequently, the clocked half-rail differential logic circuit 100 that is shown in FIG. 1A is simply used for illustrative purposes.
Clocked half-rail differential logic circuit 100 had two modes, or phases, of operation; a pre-charge phase and an evaluation phase. In one embodiment of a clocked half-rail differential logic circuit 100, in the pre-charge phase, the signal CLK was low or a digital xe2x80x9c0xe2x80x9d and the signal CLKBAR was high or a digital xe2x80x9c1xe2x80x9d. Consequently, first PFET 101 and second NFET 125 were not conducting or were xe2x80x9coffxe2x80x9d and logic block 123 was isolated from first supply voltage 102 and second supply voltage 128. In addition, during the pre-charge phase, first NFET 109 was conducting or was xe2x80x9conxe2x80x9d and, therefore, OUT terminal 111 was shorted to OUTBAR terminal 113. Consequently, the supply voltage to logic block 123 was approximately half the supply voltage 102, i.e., for a first supply voltage 102 of Vdd and a second supply voltage 128 of ground, logic block 123 operated at around Vdd/2. During pre-charge, second and third PFETs 105 and 107 were typically not performing any function.
In one embodiment of a clocked half-rail differential logic circuit 100, in the evaluation phase, the signal CLK was high or a digital xe2x80x9c1xe2x80x9d and the signal CLKBAR was low or a digital xe2x80x9c0xe2x80x9d. Consequently, first PFET 101 and second NFET 125 were conducting or were xe2x80x9conxe2x80x9d and first NFET 109 was not conducting or was xe2x80x9coffxe2x80x9d. Consequently, depending on the particular logic in logic block 123, either second PFET 105, or third PFET 107, was conducting or was xe2x80x9conxe2x80x9d and the other of second PFET 105, or third PFET 107, was not conducting or was xe2x80x9coffxe2x80x9d. As a result, either OUT terminal 111 went from approximately half first supply voltage 102 to approximately second supply voltage 128 or OUTBAR terminal 113 went from approximately half first supply voltage 102 to approximately first supply voltage 102, i.e., for a first supply voltage 102 of Vdd and a second supply voltage 128 of ground, OUT terminal 111 went from approximately Vdd/2 to zero and OUTBAR terminal 113 went from approximately Vdd/2 to Vdd.
Clocked half-rail differential logic circuits 100 marked a significant improvement over prior art half-rail logic circuits in part because clocked half-rail differential logic circuit 100 does not require the complex control circuitry of prior art half-rail differential logic circuits and is therefore simpler, saves space and is more reliable than prior art half-rail differential logic circuits. As a result, clocked half-rail differential logic circuits 100 are better suited to the present electronics market that stresses portability, compact size, lightweight and the capability for prolonged remote operation. However, clocked half-rail differential logic circuit 100 has some limitations.
For instance, as noted above, since clocked half-rail differential logic circuit 100 was a dual rail logic circuit, requiring an output OUT 111 and a complementary output OUTBAR 113, in the prior art, logic block 123 had to include both a base logic function, via base logic portion 123A of logic block 123, such as an AND gate, OR gate, XOR gate, etc. and the complementary logic function, via complementary logic portion 123B of logic block 123, such as a NAND gate, NOR gate, XNOR gate, etc.
FIG. 1B shows one particular embodiment of a clocked half-rail differential logic circuit 100A that includes a base logic portion 123A that is an AND gate and a complementary logic portion 123B that is a NAND gate. As shown in FIG. 1B, AND gate 123A includes NFET 161 and NFET 163 connected in series. Input 151 is coupled to the control electrode, or gate, of NFET 161 and input 153 is coupled to the control electrode or gate of NFET 163. As also shown in FIG. 1B, NAND gate 123A includes NFET 171 and NFET 173 connected in parallel. Input 151BAR is coupled to the control electrode, or gate, of NFET 171 and input 153BAR is coupled to the control electrode or gate of NFET 173. Consequently, in the prior art, four transistors were required to provide the output OUT 111 and its complementary output OUTBAR 113.
This need in the prior art to include both a base logic function and its complementary logic function resulted in an increase in power usage, an increase in space used, an increase in design complexity, and an increase in heat production.
In addition, clocked half-rail differential logic circuit 100 worked very well under conditions of a light load, for instance under conditions where fan out was less than four. However, clocked half-rail differential logic circuit 100 was less useful under conditions of a heavy load, for instance, in cases where fan out exceeded four. The shortcomings of clocked half-rail differential logic circuit 100 arose primarily because under heavy load conditions logic block 123, and the transistors and components making up logic block 123, had to be increased in size to act as a driver for the next stage in the cascade. This in turn meant that logic block 123 was large, slow and inefficient. The problem was further aggravated as additional clocked half-rail differential logic circuits 100 were cascaded together to form the large chains commonly used in the industry. Consequently, the full potential of clocked half-rail differential logic circuit 100 was not realized and its use was narrowly limited to light load applications.
What is needed is a method and apparatus for creating clocked half-rail differential logic circuits that use less power, generate less heat, require less space, are simpler in design, and that are capable of efficient use under heavy loads so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.
According to the invention, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic portions. According to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output OUTBAR. Consequently, clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention use less power and, therefore, generate less heat, require less space, and are simpler in design so that they are more flexible, more space efficient and more reliable than prior art half-rail differential logic circuits.
In addition, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention include a sense amplifier circuit that is triggered by the delayed clock of the following stage, i.e., the clock input to the sense amplifier circuit of the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention is additionally delayed with respect to the delayed clock that drives the clocked half-rail logic. The addition of the sense amplifier circuit, and second delayed clock signal, according to the invention, allows the sense amplifier circuit to act as the driver and therefore there is no need for increasing the size of the logic block, and the transistors and components making up the logic block, to provide the driver function. Consequently, the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art half-rail differential logic circuits.
The clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention can be cascaded together to form the chains commonly used in the industry. When the clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention are cascaded together, the advantages of the clocked half-rail differential logic circuits of the invention are particularly evident and the gains in terms of power efficiency, size reduction, and flexibility are further pronounced.
One embodiment of the invention is a clocked half-rail differential logic circuit with single-rail logic and sense amplifier that includes a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and a clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a first transistor including a first transistor first flow electrode, a first transistor second flow electrode and a first transistor control electrode. The first transistor first flow electrode is coupled to a first supply voltage.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a second transistor, the second transistor including a second transistor first flow electrode, a second transistor second flow electrode and a second transistor control electrode. The first transistor second flow electrode is coupled to the second transistor first flow electrode and the second transistor second flow electrode is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a third transistor, the third transistor including a third transistor first flow electrode, a third transistor second flow electrode and a third transistor control electrode. The first transistor second flow electrode is coupled to the third transistor first flow electrode and the third transistor second flow electrode is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a fourth transistor, the fourth transistor including a fourth transistor first flow electrode, a fourth transistor second flow electrode and a fourth transistor control electrode. The second transistor control electrode is coupled to the fourth transistor first flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal. The third transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a base logic portion, the base logic portion including a base logic portion first input terminal, a base logic portion second input terminal, a base logic portion OUT terminal, and a base logic portion fourth terminal. The base logic portion OUT terminal is coupled to the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a fifth transistor, the fifth transistor including a fifth transistor first flow electrode, a fifth transistor second flow electrode and a fifth transistor control electrode. The fifth transistor first flow electrode is coupled to the base logic portion fourth terminal and the fifth transistor second flow electrode is coupled to a second supply voltage.
The clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a complementary output transistor, the complementary output transistor including a complementary output transistor first flow electrode, a complementary output transistor second flow electrode and a complementary output transistor control electrode. According to the invention, the complementary output transistor first flow electrode is coupled to the second flow electrode of the third transistor and the OUTBAR terminal of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier. The complementary output transistor second flow electrode is coupled to the first flow electrode of the fifth transistor. The complementary output transistor control electrode is coupled to the second flow electrode of the fourth transistor and the OUT terminal of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier.
In one embodiment of the invention, a first clock signal CLKA is coupled to the fifth transistor control electrode. A first clock-not signal CLKABAR is coupled to the first transistor control electrode and the fourth transistor control electrode.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a sense amplifier circuit coupled between the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier includes a sixth transistor, the sixth transistor including a sixth transistor first flow electrode, a sixth transistor second flow electrode and a sixth transistor control electrode. The second transistor second flow electrode is coupled to the sixth transistor first flow electrode. The sixth transistor second flow electrode is coupled to a first node. The sixth transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUTBAR terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit with single-rail logic and sense amplifier also includes a seventh transistor, the seventh transistor including a seventh transistor first flow electrode, a seventh transistor second flow electrode and a seventh transistor control electrode. The third transistor second flow electrode is coupled to the seventh transistor first flow electrode. The seventh transistor second flow electrode is coupled to the first node. The seventh transistor control electrode is coupled to the fourth transistor second flow electrode and the clocked half-rail differential logic circuit with single-rail logic and sense amplifier OUT terminal.
In one embodiment of the invention, the clocked half-rail differential logic circuit sense amplifier circuit also includes an eighth transistor, the eighth transistor including an eighth transistor first flow electrode, an eighth transistor second flow electrode and an eighth transistor control electrode. The eighth transistor first flow electrode is coupled to the first node and the eighth transistor second flow electrode is coupled to a second supply voltage. A second clock signal CLKB is coupled to the eighth transistor control electrode of the clocked half-rail differential logic circuit with single-rail logic and sense amplifier. In one embodiment of the invention, the second clock signal CLKB is delayed a predetermined time with respect to the first clock signal CLKA.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.